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@@ -9,21 +9,13 @@
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* Use LP timer on Kinetises, TIM14 on STM32F0.
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*/
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-#if defined(KL2x) || defined(K20x)
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-
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-/* Use Low Power Timer (LPTMR) */
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-# define TIMER_INTERRUPT_VECTOR KINETIS_LPTMR0_IRQ_VECTOR
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-# define RESET_COUNTER LPTMR0->CSR |= LPTMRx_CSR_TCF
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-
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-#elif defined(STM32F0XX)
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-
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-/* Use TIM14 manually */
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-# define TIMER_INTERRUPT_VECTOR STM32_TIM14_HANDLER
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-# define RESET_COUNTER STM32_TIM14->SR &= ~STM32_TIM_SR_UIF
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-
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+#ifndef SLEEP_LED_GPT_DRIVER
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+# if defined(STM32F0XX)
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+# define SLEEP_LED_GPT_DRIVER GPTD14
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+# endif
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#endif
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-#if defined(KL2x) || defined(K20x) || defined(STM32F0XX) /* common parts for timers/interrupts */
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+#if defined(KL2x) || defined(K20x) || defined(SLEEP_LED_GPT_DRIVER) /* common parts for timers/interrupts */
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/* Breathing Sleep LED brighness(PWM On period) table
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* (64[steps] * 4[duration]) / 64[PWM periods/s] = 4 second breath cycle
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@@ -33,10 +25,7 @@
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*/
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static const uint8_t breathing_table[64] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 4, 6, 10, 15, 23, 32, 44, 58, 74, 93, 113, 135, 157, 179, 199, 218, 233, 245, 252, 255, 252, 245, 233, 218, 199, 179, 157, 135, 113, 93, 74, 58, 44, 32, 23, 15, 10, 6, 4, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
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-/* interrupt handler */
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-OSAL_IRQ_HANDLER(TIMER_INTERRUPT_VECTOR) {
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- OSAL_IRQ_PROLOGUE();
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-
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+void sleep_led_timer_callback(void) {
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/* Software PWM
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* timer:1111 1111 1111 1111
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* \_____/\/ \_______/____ count(0-255)
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@@ -64,17 +53,16 @@ OSAL_IRQ_HANDLER(TIMER_INTERRUPT_VECTOR) {
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if (timer.pwm.count == breathing_table[timer.pwm.index]) {
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led_set(0);
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}
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-
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- /* Reset the counter */
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- RESET_COUNTER;
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-
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- OSAL_IRQ_EPILOGUE();
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}
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#endif /* common parts for known platforms */
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#if defined(KL2x) || defined(K20x) /* platform selection: familiar Kinetis chips */
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+/* Use Low Power Timer (LPTMR) */
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+# define TIMER_INTERRUPT_VECTOR KINETIS_LPTMR0_IRQ_VECTOR
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+# define RESET_COUNTER LPTMR0->CSR |= LPTMRx_CSR_TCF
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+
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/* LPTMR clock options */
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# define LPTMR_CLOCK_MCGIRCLK 0 /* 4MHz clock */
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# define LPTMR_CLOCK_LPO 1 /* 1kHz clock */
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@@ -86,6 +74,18 @@ OSAL_IRQ_HANDLER(TIMER_INTERRUPT_VECTOR) {
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# define SIM_SCGC5_LPTMR SIM_SCGC5_LPTIMER
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# endif
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+/* interrupt handler */
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+OSAL_IRQ_HANDLER(TIMER_INTERRUPT_VECTOR) {
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+ OSAL_IRQ_PROLOGUE();
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+
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+ sleep_led_timer_callback();
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+
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+ /* Reset the counter */
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+ RESET_COUNTER;
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+
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+ OSAL_IRQ_EPILOGUE();
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+}
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+
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/* Initialise the timer */
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void sleep_led_init(void) {
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/* Make sure the clock to the LPTMR is enabled */
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@@ -159,45 +159,23 @@ void sleep_led_toggle(void) {
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LPTMR0->CSR ^= LPTMRx_CSR_TEN;
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}
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-#elif defined(STM32F0XX) /* platform selection: STM32F0XX */
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-
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-/* Initialise the timer */
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-void sleep_led_init(void) {
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- /* enable clock */
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- rccEnableTIM14(FALSE); /* low power enable = FALSE */
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- rccResetTIM14();
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-
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- /* prescale */
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- /* Assuming 48MHz internal clock */
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- /* getting cca 65484 irqs/sec */
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- STM32_TIM14->PSC = 733;
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+#elif defined(SLEEP_LED_GPT_DRIVER)
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- /* auto-reload */
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- /* 0 => interrupt every time */
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- STM32_TIM14->ARR = 3;
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+static void gptTimerCallback(GPTDriver *gptp) {
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+ (void)gptp;
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+ sleep_led_timer_callback();
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+}
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- /* enable counter update event interrupt */
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- STM32_TIM14->DIER |= STM32_TIM_DIER_UIE;
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+static const GPTConfig gptcfg = {1000000, gptTimerCallback, 0, 0};
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- /* register interrupt vector */
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- nvicEnableVector(STM32_TIM14_NUMBER, 2); /* vector, priority */
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-}
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+/* Initialise the timer */
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+void sleep_led_init(void) { gptStart(&SLEEP_LED_GPT_DRIVER, &gptcfg); }
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-void sleep_led_enable(void) {
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- /* Enable the timer */
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- STM32_TIM14->CR1 = STM32_TIM_CR1_CEN | STM32_TIM_CR1_URS;
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- /* URS => update event only on overflow; setting UG bit disabled */
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-}
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+void sleep_led_enable(void) { gptStartContinuous(&SLEEP_LED_GPT_DRIVER, gptcfg.frequency / 0xFFFF); }
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-void sleep_led_disable(void) {
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- /* Disable the timer */
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- STM32_TIM14->CR1 = 0;
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-}
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+void sleep_led_disable(void) { gptStopTimer(&SLEEP_LED_GPT_DRIVER); }
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-void sleep_led_toggle(void) {
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- /* Toggle the timer */
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- STM32_TIM14->CR1 ^= STM32_TIM_CR1_CEN;
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-}
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+void sleep_led_toggle(void) { (SLEEP_LED_GPT_DRIVER.state == GPT_READY) ? sleep_led_enable() : sleep_led_disable(); }
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#else /* platform selection: not on familiar chips */
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Joel Challis