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@@ -0,0 +1,546 @@
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+/*
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+ * WARNING: be careful changing this code, it is very timing dependent
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+ *
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+ * 2018-10-28 checked
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+ * avr-gcc 4.9.2
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+ * avr-gcc 5.4.0
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+ * avr-gcc 7.3.0
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+ */
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+
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+#ifndef F_CPU
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+#define F_CPU 16000000
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+#endif
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+
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+#include <avr/io.h>
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+#include <avr/interrupt.h>
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+#include <util/delay.h>
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+#include <stddef.h>
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+#include <stdbool.h>
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+#include "serial.h"
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+//#include <pro_micro.h>
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+
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+#ifdef SOFT_SERIAL_PIN
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+
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+#ifdef __AVR_ATmega32U4__
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+ // if using ATmega32U4 I2C, can not use PD0 and PD1 in soft serial.
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+ #ifdef USE_AVR_I2C
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+ #if SOFT_SERIAL_PIN == D0 || SOFT_SERIAL_PIN == D1
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+ #error Using ATmega32U4 I2C, so can not use PD0, PD1
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+ #endif
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+ #endif
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+
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+ #if SOFT_SERIAL_PIN >= D0 && SOFT_SERIAL_PIN <= D3
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+ #define SERIAL_PIN_DDR DDRD
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+ #define SERIAL_PIN_PORT PORTD
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+ #define SERIAL_PIN_INPUT PIND
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+ #if SOFT_SERIAL_PIN == D0
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+ #define SERIAL_PIN_MASK _BV(PD0)
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+ #define EIMSK_BIT _BV(INT0)
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+ #define EICRx_BIT (~(_BV(ISC00) | _BV(ISC01)))
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+ #define SERIAL_PIN_INTERRUPT INT0_vect
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+ #elif SOFT_SERIAL_PIN == D1
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+ #define SERIAL_PIN_MASK _BV(PD1)
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+ #define EIMSK_BIT _BV(INT1)
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+ #define EICRx_BIT (~(_BV(ISC10) | _BV(ISC11)))
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+ #define SERIAL_PIN_INTERRUPT INT1_vect
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+ #elif SOFT_SERIAL_PIN == D2
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+ #define SERIAL_PIN_MASK _BV(PD2)
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+ #define EIMSK_BIT _BV(INT2)
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+ #define EICRx_BIT (~(_BV(ISC20) | _BV(ISC21)))
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+ #define SERIAL_PIN_INTERRUPT INT2_vect
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+ #elif SOFT_SERIAL_PIN == D3
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+ #define SERIAL_PIN_MASK _BV(PD3)
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+ #define EIMSK_BIT _BV(INT3)
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+ #define EICRx_BIT (~(_BV(ISC30) | _BV(ISC31)))
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+ #define SERIAL_PIN_INTERRUPT INT3_vect
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+ #endif
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+ #elif SOFT_SERIAL_PIN == E6
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+ #define SERIAL_PIN_DDR DDRE
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+ #define SERIAL_PIN_PORT PORTE
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+ #define SERIAL_PIN_INPUT PINE
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+ #define SERIAL_PIN_MASK _BV(PE6)
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+ #define EIMSK_BIT _BV(INT6)
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+ #define EICRx_BIT (~(_BV(ISC60) | _BV(ISC61)))
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+ #define SERIAL_PIN_INTERRUPT INT6_vect
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+ #else
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+ #error invalid SOFT_SERIAL_PIN value
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+ #endif
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+
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+#else
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+ #error serial.c now support ATmega32U4 only
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+#endif
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+
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+#define ALWAYS_INLINE __attribute__((always_inline))
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+#define NO_INLINE __attribute__((noinline))
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+#define _delay_sub_us(x) __builtin_avr_delay_cycles(x)
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+
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+// parity check
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+#define ODD_PARITY 1
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+#define EVEN_PARITY 0
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+#define PARITY EVEN_PARITY
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+
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+#ifdef SERIAL_DELAY
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+ // custom setup in config.h
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+ // #define TID_SEND_ADJUST 2
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+ // #define SERIAL_DELAY 6 // micro sec
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+ // #define READ_WRITE_START_ADJUST 30 // cycles
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+ // #define READ_WRITE_WIDTH_ADJUST 8 // cycles
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+#else
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+// ============ Standard setups ============
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+
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+#ifndef SELECT_SOFT_SERIAL_SPEED
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+#define SELECT_SOFT_SERIAL_SPEED 1
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+// 0: about 189kbps (Experimental only)
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+// 1: about 137kbps (default)
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+// 2: about 75kbps
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+// 3: about 39kbps
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+// 4: about 26kbps
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+// 5: about 20kbps
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+#endif
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+
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+#if __GNUC__ < 6
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+ #define TID_SEND_ADJUST 14
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+#else
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+ #define TID_SEND_ADJUST 2
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+#endif
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+
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+#if SELECT_SOFT_SERIAL_SPEED == 0
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+ // Very High speed
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+ #define SERIAL_DELAY 4 // micro sec
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+ #if __GNUC__ < 6
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+ #define READ_WRITE_START_ADJUST 33 // cycles
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+ #define READ_WRITE_WIDTH_ADJUST 3 // cycles
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+ #else
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+ #define READ_WRITE_START_ADJUST 34 // cycles
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+ #define READ_WRITE_WIDTH_ADJUST 7 // cycles
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+ #endif
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+#elif SELECT_SOFT_SERIAL_SPEED == 1
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+ // High speed
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+ #define SERIAL_DELAY 6 // micro sec
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+ #if __GNUC__ < 6
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+ #define READ_WRITE_START_ADJUST 30 // cycles
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+ #define READ_WRITE_WIDTH_ADJUST 3 // cycles
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+ #else
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+ #define READ_WRITE_START_ADJUST 33 // cycles
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+ #define READ_WRITE_WIDTH_ADJUST 7 // cycles
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+ #endif
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+#elif SELECT_SOFT_SERIAL_SPEED == 2
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+ // Middle speed
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+ #define SERIAL_DELAY 12 // micro sec
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+ #define READ_WRITE_START_ADJUST 30 // cycles
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+ #if __GNUC__ < 6
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+ #define READ_WRITE_WIDTH_ADJUST 3 // cycles
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+ #else
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+ #define READ_WRITE_WIDTH_ADJUST 7 // cycles
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+ #endif
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+#elif SELECT_SOFT_SERIAL_SPEED == 3
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+ // Low speed
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+ #define SERIAL_DELAY 24 // micro sec
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+ #define READ_WRITE_START_ADJUST 30 // cycles
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+ #if __GNUC__ < 6
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+ #define READ_WRITE_WIDTH_ADJUST 3 // cycles
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+ #else
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+ #define READ_WRITE_WIDTH_ADJUST 7 // cycles
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+ #endif
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+#elif SELECT_SOFT_SERIAL_SPEED == 4
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+ // Very Low speed
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+ #define SERIAL_DELAY 36 // micro sec
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+ #define READ_WRITE_START_ADJUST 30 // cycles
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+ #if __GNUC__ < 6
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+ #define READ_WRITE_WIDTH_ADJUST 3 // cycles
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+ #else
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+ #define READ_WRITE_WIDTH_ADJUST 7 // cycles
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+ #endif
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+#elif SELECT_SOFT_SERIAL_SPEED == 5
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+ // Ultra Low speed
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+ #define SERIAL_DELAY 48 // micro sec
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+ #define READ_WRITE_START_ADJUST 30 // cycles
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+ #if __GNUC__ < 6
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+ #define READ_WRITE_WIDTH_ADJUST 3 // cycles
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+ #else
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+ #define READ_WRITE_WIDTH_ADJUST 7 // cycles
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+ #endif
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+#else
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+#error invalid SELECT_SOFT_SERIAL_SPEED value
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+#endif /* SELECT_SOFT_SERIAL_SPEED */
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+#endif /* SERIAL_DELAY */
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+
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+#define SERIAL_DELAY_HALF1 (SERIAL_DELAY/2)
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+#define SERIAL_DELAY_HALF2 (SERIAL_DELAY - SERIAL_DELAY/2)
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+
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+#define SLAVE_INT_WIDTH_US 1
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+#ifndef SERIAL_USE_MULTI_TRANSACTION
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+ #define SLAVE_INT_RESPONSE_TIME SERIAL_DELAY
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+#else
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+ #define SLAVE_INT_ACK_WIDTH_UNIT 2
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+ #define SLAVE_INT_ACK_WIDTH 4
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+#endif
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+
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+static SSTD_t *Transaction_table = NULL;
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+static uint8_t Transaction_table_size = 0;
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+
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+inline static void serial_delay(void) ALWAYS_INLINE;
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+inline static
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+void serial_delay(void) {
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+ _delay_us(SERIAL_DELAY);
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+}
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+
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+inline static void serial_delay_half1(void) ALWAYS_INLINE;
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+inline static
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+void serial_delay_half1(void) {
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+ _delay_us(SERIAL_DELAY_HALF1);
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+}
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+
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+inline static void serial_delay_half2(void) ALWAYS_INLINE;
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+inline static
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+void serial_delay_half2(void) {
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+ _delay_us(SERIAL_DELAY_HALF2);
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+}
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+
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+inline static void serial_output(void) ALWAYS_INLINE;
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+inline static
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+void serial_output(void) {
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+ SERIAL_PIN_DDR |= SERIAL_PIN_MASK;
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+}
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+
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+// make the serial pin an input with pull-up resistor
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+inline static void serial_input_with_pullup(void) ALWAYS_INLINE;
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+inline static
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+void serial_input_with_pullup(void) {
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+ SERIAL_PIN_DDR &= ~SERIAL_PIN_MASK;
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+ SERIAL_PIN_PORT |= SERIAL_PIN_MASK;
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+}
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+
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+inline static uint8_t serial_read_pin(void) ALWAYS_INLINE;
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+inline static
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+uint8_t serial_read_pin(void) {
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+ return !!(SERIAL_PIN_INPUT & SERIAL_PIN_MASK);
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+}
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+
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+inline static void serial_low(void) ALWAYS_INLINE;
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+inline static
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+void serial_low(void) {
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+ SERIAL_PIN_PORT &= ~SERIAL_PIN_MASK;
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+}
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+
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+inline static void serial_high(void) ALWAYS_INLINE;
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+inline static
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+void serial_high(void) {
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+ SERIAL_PIN_PORT |= SERIAL_PIN_MASK;
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+}
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+
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+void soft_serial_initiator_init(SSTD_t *sstd_table, int sstd_table_size)
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+{
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+ Transaction_table = sstd_table;
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+ Transaction_table_size = (uint8_t)sstd_table_size;
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+ serial_output();
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+ serial_high();
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+}
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+
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+void soft_serial_target_init(SSTD_t *sstd_table, int sstd_table_size)
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+{
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+ Transaction_table = sstd_table;
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+ Transaction_table_size = (uint8_t)sstd_table_size;
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+ serial_input_with_pullup();
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+
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+ // Enable INT0-INT3,INT6
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+ EIMSK |= EIMSK_BIT;
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+#if SERIAL_PIN_MASK == _BV(PE6)
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+ // Trigger on falling edge of INT6
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+ EICRB &= EICRx_BIT;
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+#else
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+ // Trigger on falling edge of INT0-INT3
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+ EICRA &= EICRx_BIT;
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+#endif
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+}
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+
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+// Used by the sender to synchronize timing with the reciver.
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+static void sync_recv(void) NO_INLINE;
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+static
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+void sync_recv(void) {
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+ for (uint8_t i = 0; i < SERIAL_DELAY*5 && serial_read_pin(); i++ ) {
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+ }
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+ // This shouldn't hang if the target disconnects because the
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+ // serial line will float to high if the target does disconnect.
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+ while (!serial_read_pin());
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+}
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+
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+// Used by the reciver to send a synchronization signal to the sender.
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+static void sync_send(void) NO_INLINE;
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+static
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+void sync_send(void) {
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+ serial_low();
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+ serial_delay();
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+ serial_high();
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+}
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+
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+// Reads a byte from the serial line
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+static uint8_t serial_read_chunk(uint8_t *pterrcount, uint8_t bit) NO_INLINE;
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+static uint8_t serial_read_chunk(uint8_t *pterrcount, uint8_t bit) {
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+ uint8_t byte, i, p, pb;
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+
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+ _delay_sub_us(READ_WRITE_START_ADJUST);
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+ for( i = 0, byte = 0, p = PARITY; i < bit; i++ ) {
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+ serial_delay_half1(); // read the middle of pulses
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+ if( serial_read_pin() ) {
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+ byte = (byte << 1) | 1; p ^= 1;
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+ } else {
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+ byte = (byte << 1) | 0; p ^= 0;
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+ }
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+ _delay_sub_us(READ_WRITE_WIDTH_ADJUST);
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+ serial_delay_half2();
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+ }
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+ /* recive parity bit */
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+ serial_delay_half1(); // read the middle of pulses
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+ pb = serial_read_pin();
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+ _delay_sub_us(READ_WRITE_WIDTH_ADJUST);
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+ serial_delay_half2();
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+
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+ *pterrcount += (p != pb)? 1 : 0;
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+
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+ return byte;
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+}
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+
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+// Sends a byte with MSB ordering
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+void serial_write_chunk(uint8_t data, uint8_t bit) NO_INLINE;
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+void serial_write_chunk(uint8_t data, uint8_t bit) {
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+ uint8_t b, p;
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+ for( p = PARITY, b = 1<<(bit-1); b ; b >>= 1) {
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+ if(data & b) {
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+ serial_high(); p ^= 1;
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+ } else {
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+ serial_low(); p ^= 0;
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+ }
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+ serial_delay();
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+ }
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+ /* send parity bit */
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+ if(p & 1) { serial_high(); }
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+ else { serial_low(); }
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+ serial_delay();
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+
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+ serial_low(); // sync_send() / senc_recv() need raise edge
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+}
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+
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+static void serial_send_packet(uint8_t *buffer, uint8_t size) NO_INLINE;
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+static
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+void serial_send_packet(uint8_t *buffer, uint8_t size) {
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+ for (uint8_t i = 0; i < size; ++i) {
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+ uint8_t data;
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+ data = buffer[i];
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+ sync_send();
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+ serial_write_chunk(data,8);
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+ }
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+}
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+
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+static uint8_t serial_recive_packet(uint8_t *buffer, uint8_t size) NO_INLINE;
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+static
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+uint8_t serial_recive_packet(uint8_t *buffer, uint8_t size) {
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+ uint8_t pecount = 0;
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+ for (uint8_t i = 0; i < size; ++i) {
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+ uint8_t data;
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+ sync_recv();
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+ data = serial_read_chunk(&pecount, 8);
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+ buffer[i] = data;
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+ }
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+ return pecount == 0;
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+}
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+
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+inline static
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+void change_sender2reciver(void) {
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+ sync_send(); //0
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+ serial_delay_half1(); //1
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+ serial_low(); //2
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+ serial_input_with_pullup(); //2
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+ serial_delay_half1(); //3
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+}
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+
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+inline static
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+void change_reciver2sender(void) {
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+ sync_recv(); //0
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+ serial_delay(); //1
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+ serial_low(); //3
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+ serial_output(); //3
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+ serial_delay_half1(); //4
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+}
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+
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+static inline uint8_t nibble_bits_count(uint8_t bits)
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+{
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+ bits = (bits & 0x5) + (bits >> 1 & 0x5);
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+ bits = (bits & 0x3) + (bits >> 2 & 0x3);
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+ return bits;
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+}
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+
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+// interrupt handle to be used by the target device
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+ISR(SERIAL_PIN_INTERRUPT) {
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+
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+#ifndef SERIAL_USE_MULTI_TRANSACTION
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+ serial_low();
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+ serial_output();
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+ SSTD_t *trans = Transaction_table;
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+#else
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+ // recive transaction table index
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+ uint8_t tid, bits;
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+ uint8_t pecount = 0;
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+ sync_recv();
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+ bits = serial_read_chunk(&pecount,7);
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+ tid = bits>>3;
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+ bits = (bits&7) != nibble_bits_count(tid);
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+ if( bits || pecount> 0 || tid > Transaction_table_size ) {
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+ return;
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+ }
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+ serial_delay_half1();
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+
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+ serial_high(); // response step1 low->high
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+ serial_output();
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+ _delay_sub_us(SLAVE_INT_ACK_WIDTH_UNIT*SLAVE_INT_ACK_WIDTH);
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+ SSTD_t *trans = &Transaction_table[tid];
|
|
|
+ serial_low(); // response step2 ack high->low
|
|
|
+#endif
|
|
|
+
|
|
|
+ // target send phase
|
|
|
+ if( trans->target2initiator_buffer_size > 0 )
|
|
|
+ serial_send_packet((uint8_t *)trans->target2initiator_buffer,
|
|
|
+ trans->target2initiator_buffer_size);
|
|
|
+ // target switch to input
|
|
|
+ change_sender2reciver();
|
|
|
+
|
|
|
+ // target recive phase
|
|
|
+ if( trans->initiator2target_buffer_size > 0 ) {
|
|
|
+ if (serial_recive_packet((uint8_t *)trans->initiator2target_buffer,
|
|
|
+ trans->initiator2target_buffer_size) ) {
|
|
|
+ *trans->status = TRANSACTION_ACCEPTED;
|
|
|
+ } else {
|
|
|
+ *trans->status = TRANSACTION_DATA_ERROR;
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ *trans->status = TRANSACTION_ACCEPTED;
|
|
|
+ }
|
|
|
+
|
|
|
+ sync_recv(); //weit initiator output to high
|
|
|
+}
|
|
|
+
|
|
|
+/////////
|
|
|
+// start transaction by initiator
|
|
|
+//
|
|
|
+// int soft_serial_transaction(int sstd_index)
|
|
|
+//
|
|
|
+// Returns:
|
|
|
+// TRANSACTION_END
|
|
|
+// TRANSACTION_NO_RESPONSE
|
|
|
+// TRANSACTION_DATA_ERROR
|
|
|
+// this code is very time dependent, so we need to disable interrupts
|
|
|
+#ifndef SERIAL_USE_MULTI_TRANSACTION
|
|
|
+int soft_serial_transaction(void) {
|
|
|
+ SSTD_t *trans = Transaction_table;
|
|
|
+#else
|
|
|
+int soft_serial_transaction(int sstd_index) {
|
|
|
+ if( sstd_index > Transaction_table_size )
|
|
|
+ return TRANSACTION_TYPE_ERROR;
|
|
|
+ SSTD_t *trans = &Transaction_table[sstd_index];
|
|
|
+#endif
|
|
|
+ cli();
|
|
|
+
|
|
|
+ // signal to the target that we want to start a transaction
|
|
|
+ serial_output();
|
|
|
+ serial_low();
|
|
|
+ _delay_us(SLAVE_INT_WIDTH_US);
|
|
|
+
|
|
|
+#ifndef SERIAL_USE_MULTI_TRANSACTION
|
|
|
+ // wait for the target response
|
|
|
+ serial_input_with_pullup();
|
|
|
+ _delay_us(SLAVE_INT_RESPONSE_TIME);
|
|
|
+
|
|
|
+ // check if the target is present
|
|
|
+ if (serial_read_pin()) {
|
|
|
+ // target failed to pull the line low, assume not present
|
|
|
+ serial_output();
|
|
|
+ serial_high();
|
|
|
+ *trans->status = TRANSACTION_NO_RESPONSE;
|
|
|
+ sei();
|
|
|
+ return TRANSACTION_NO_RESPONSE;
|
|
|
+ }
|
|
|
+
|
|
|
+#else
|
|
|
+ // send transaction table index
|
|
|
+ int tid = (sstd_index<<3) | (7 & nibble_bits_count(sstd_index));
|
|
|
+ sync_send();
|
|
|
+ _delay_sub_us(TID_SEND_ADJUST);
|
|
|
+ serial_write_chunk(tid, 7);
|
|
|
+ serial_delay_half1();
|
|
|
+
|
|
|
+ // wait for the target response (step1 low->high)
|
|
|
+ serial_input_with_pullup();
|
|
|
+ while( !serial_read_pin() ) {
|
|
|
+ _delay_sub_us(2);
|
|
|
+ }
|
|
|
+
|
|
|
+ // check if the target is present (step2 high->low)
|
|
|
+ for( int i = 0; serial_read_pin(); i++ ) {
|
|
|
+ if (i > SLAVE_INT_ACK_WIDTH + 1) {
|
|
|
+ // slave failed to pull the line low, assume not present
|
|
|
+ serial_output();
|
|
|
+ serial_high();
|
|
|
+ *trans->status = TRANSACTION_NO_RESPONSE;
|
|
|
+ sei();
|
|
|
+ return TRANSACTION_NO_RESPONSE;
|
|
|
+ }
|
|
|
+ _delay_sub_us(SLAVE_INT_ACK_WIDTH_UNIT);
|
|
|
+ }
|
|
|
+#endif
|
|
|
+
|
|
|
+ // initiator recive phase
|
|
|
+ // if the target is present syncronize with it
|
|
|
+ if( trans->target2initiator_buffer_size > 0 ) {
|
|
|
+ if (!serial_recive_packet((uint8_t *)trans->target2initiator_buffer,
|
|
|
+ trans->target2initiator_buffer_size) ) {
|
|
|
+ serial_output();
|
|
|
+ serial_high();
|
|
|
+ *trans->status = TRANSACTION_DATA_ERROR;
|
|
|
+ sei();
|
|
|
+ return TRANSACTION_DATA_ERROR;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ // initiator switch to output
|
|
|
+ change_reciver2sender();
|
|
|
+
|
|
|
+ // initiator send phase
|
|
|
+ if( trans->initiator2target_buffer_size > 0 ) {
|
|
|
+ serial_send_packet((uint8_t *)trans->initiator2target_buffer,
|
|
|
+ trans->initiator2target_buffer_size);
|
|
|
+ }
|
|
|
+
|
|
|
+ // always, release the line when not in use
|
|
|
+ sync_send();
|
|
|
+
|
|
|
+ *trans->status = TRANSACTION_END;
|
|
|
+ sei();
|
|
|
+ return TRANSACTION_END;
|
|
|
+}
|
|
|
+
|
|
|
+#ifdef SERIAL_USE_MULTI_TRANSACTION
|
|
|
+int soft_serial_get_and_clean_status(int sstd_index) {
|
|
|
+ SSTD_t *trans = &Transaction_table[sstd_index];
|
|
|
+ cli();
|
|
|
+ int retval = *trans->status;
|
|
|
+ *trans->status = 0;;
|
|
|
+ sei();
|
|
|
+ return retval;
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#endif
|
|
|
+
|
|
|
+// Helix serial.c history
|
|
|
+// 2018-1-29 fork from let's split and add PD2, modify sync_recv() (#2308, bceffdefc)
|
|
|
+// 2018-6-28 bug fix master to slave comm and speed up (#3255, 1038bbef4)
|
|
|
+// (adjusted with avr-gcc 4.9.2)
|
|
|
+// 2018-7-13 remove USE_SERIAL_PD2 macro (#3374, f30d6dd78)
|
|
|
+// (adjusted with avr-gcc 4.9.2)
|
|
|
+// 2018-8-11 add support multi-type transaction (#3608, feb5e4aae)
|
|
|
+// (adjusted with avr-gcc 4.9.2)
|
|
|
+// 2018-10-21 fix serial and RGB animation conflict (#4191, 4665e4fff)
|
|
|
+// (adjusted with avr-gcc 7.3.0)
|
|
|
+// 2018-10-28 re-adjust compiler depend value of delay (#4269, 8517f8a66)
|
|
|
+// (adjusted with avr-gcc 5.4.0, 7.3.0)
|
|
|
+// 2018-12-17 copy to TOP/quantum/split_common/ and remove backward compatibility code (#4669)
|