serial.c 18 KB

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  1. /*
  2. * WARNING: be careful changing this code, it is very timing dependent
  3. *
  4. * 2018-10-28 checked
  5. * avr-gcc 4.9.2
  6. * avr-gcc 5.4.0
  7. * avr-gcc 7.3.0
  8. */
  9. #ifndef F_CPU
  10. # define F_CPU 16000000
  11. #endif
  12. #include <avr/io.h>
  13. #include <avr/interrupt.h>
  14. #include <util/delay.h>
  15. #include <stddef.h>
  16. #include <stdbool.h>
  17. #include "serial.h"
  18. #ifdef SOFT_SERIAL_PIN
  19. # if !(defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB647__) || defined(__AVR_AT90USB1286__) || defined(__AVR_AT90USB1287__) || defined(__AVR_AT90USB162__) || defined(__AVR_ATmega16U2__) || defined(__AVR_ATmega32U2__) || defined(__AVR_ATmega16U4__) || defined(__AVR_ATmega32U4__))
  20. # error serial.c is not supported for the currently selected MCU
  21. # endif
  22. // if using ATmega32U4/2, AT90USBxxx I2C, can not use PD0 and PD1 in soft serial.
  23. # if defined(__AVR_ATmega16U4__) || defined(__AVR_ATmega32U4__) || defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB647__) || defined(__AVR_AT90USB1286__) || defined(__AVR_AT90USB1287__)
  24. # if defined(USE_AVR_I2C) && (SOFT_SERIAL_PIN == D0 || SOFT_SERIAL_PIN == D1)
  25. # error Using I2C, so can not use PD0, PD1
  26. # endif
  27. # endif
  28. // PD0..PD3, common config
  29. # if SOFT_SERIAL_PIN == D0
  30. # define EIMSK_BIT _BV(INT0)
  31. # define EICRx_BIT (~(_BV(ISC00) | _BV(ISC01)))
  32. # define SERIAL_PIN_INTERRUPT INT0_vect
  33. # define EICRx EICRA
  34. # elif SOFT_SERIAL_PIN == D1
  35. # define EIMSK_BIT _BV(INT1)
  36. # define EICRx_BIT (~(_BV(ISC10) | _BV(ISC11)))
  37. # define SERIAL_PIN_INTERRUPT INT1_vect
  38. # define EICRx EICRA
  39. # elif SOFT_SERIAL_PIN == D2
  40. # define EIMSK_BIT _BV(INT2)
  41. # define EICRx_BIT (~(_BV(ISC20) | _BV(ISC21)))
  42. # define SERIAL_PIN_INTERRUPT INT2_vect
  43. # define EICRx EICRA
  44. # elif SOFT_SERIAL_PIN == D3
  45. # define EIMSK_BIT _BV(INT3)
  46. # define EICRx_BIT (~(_BV(ISC30) | _BV(ISC31)))
  47. # define SERIAL_PIN_INTERRUPT INT3_vect
  48. # define EICRx EICRA
  49. # endif
  50. // ATmegaxxU2/AT90USB162 specific config
  51. # if defined(__AVR_ATmega16U2__) || defined(__AVR_ATmega32U2__) || defined(__AVR_AT90USB162__)
  52. // PD4(INT5), PD6(INT6), PD7(INT7), PC7(INT4)
  53. # if SOFT_SERIAL_PIN == D4
  54. # define EIMSK_BIT _BV(INT5)
  55. # define EICRx_BIT (~(_BV(ISC50) | _BV(ISC51)))
  56. # define SERIAL_PIN_INTERRUPT INT5_vect
  57. # define EICRx EICRB
  58. # elif SOFT_SERIAL_PIN == D6
  59. # define EIMSK_BIT _BV(INT6)
  60. # define EICRx_BIT (~(_BV(ISC60) | _BV(ISC61)))
  61. # define SERIAL_PIN_INTERRUPT INT6_vect
  62. # define EICRx EICRB
  63. # elif SOFT_SERIAL_PIN == D7
  64. # define EIMSK_BIT _BV(INT7)
  65. # define EICRx_BIT (~(_BV(ISC70) | _BV(ISC71)))
  66. # define SERIAL_PIN_INTERRUPT INT7_vect
  67. # define EICRx EICRB
  68. # elif SOFT_SERIAL_PIN == C7
  69. # define EIMSK_BIT _BV(INT4)
  70. # define EICRx_BIT (~(_BV(ISC40) | _BV(ISC41)))
  71. # define SERIAL_PIN_INTERRUPT INT4_vect
  72. # define EICRx EICRB
  73. # endif
  74. # endif
  75. // ATmegaxxU4 specific config
  76. # if defined(__AVR_ATmega16U4__) || defined(__AVR_ATmega32U4__)
  77. // PE6(INT6)
  78. # if SOFT_SERIAL_PIN == E6
  79. # define EIMSK_BIT _BV(INT6)
  80. # define EICRx_BIT (~(_BV(ISC60) | _BV(ISC61)))
  81. # define SERIAL_PIN_INTERRUPT INT6_vect
  82. # define EICRx EICRB
  83. # endif
  84. # endif
  85. // AT90USBxxx specific config
  86. # if defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB647__) || defined(__AVR_AT90USB1286__) || defined(__AVR_AT90USB1287__)
  87. // PE4..PE7(INT4..INT7)
  88. # if SOFT_SERIAL_PIN == E4
  89. # define EIMSK_BIT _BV(INT4)
  90. # define EICRx_BIT (~(_BV(ISC40) | _BV(ISC41)))
  91. # define SERIAL_PIN_INTERRUPT INT4_vect
  92. # define EICRx EICRB
  93. # elif SOFT_SERIAL_PIN == E5
  94. # define EIMSK_BIT _BV(INT5)
  95. # define EICRx_BIT (~(_BV(ISC50) | _BV(ISC51)))
  96. # define SERIAL_PIN_INTERRUPT INT5_vect
  97. # define EICRx EICRB
  98. # elif SOFT_SERIAL_PIN == E6
  99. # define EIMSK_BIT _BV(INT6)
  100. # define EICRx_BIT (~(_BV(ISC60) | _BV(ISC61)))
  101. # define SERIAL_PIN_INTERRUPT INT6_vect
  102. # define EICRx EICRB
  103. # elif SOFT_SERIAL_PIN == E7
  104. # define EIMSK_BIT _BV(INT7)
  105. # define EICRx_BIT (~(_BV(ISC70) | _BV(ISC71)))
  106. # define SERIAL_PIN_INTERRUPT INT7_vect
  107. # define EICRx EICRB
  108. # endif
  109. # endif
  110. # ifndef SERIAL_PIN_INTERRUPT
  111. # error invalid SOFT_SERIAL_PIN value
  112. # endif
  113. # define setPinInputHigh(pin) (DDRx_ADDRESS(pin) &= ~_BV((pin)&0xF), PORTx_ADDRESS(pin) |= _BV((pin)&0xF))
  114. # define setPinOutput(pin) (DDRx_ADDRESS(pin) |= _BV((pin)&0xF))
  115. # define writePinHigh(pin) (PORTx_ADDRESS(pin) |= _BV((pin)&0xF))
  116. # define writePinLow(pin) (PORTx_ADDRESS(pin) &= ~_BV((pin)&0xF))
  117. # define readPin(pin) ((bool)(PINx_ADDRESS(pin) & _BV((pin)&0xF)))
  118. # define ALWAYS_INLINE __attribute__((always_inline))
  119. # define NO_INLINE __attribute__((noinline))
  120. # define _delay_sub_us(x) __builtin_avr_delay_cycles(x)
  121. // parity check
  122. # define ODD_PARITY 1
  123. # define EVEN_PARITY 0
  124. # define PARITY EVEN_PARITY
  125. # ifdef SERIAL_DELAY
  126. // custom setup in config.h
  127. // #define TID_SEND_ADJUST 2
  128. // #define SERIAL_DELAY 6 // micro sec
  129. // #define READ_WRITE_START_ADJUST 30 // cycles
  130. // #define READ_WRITE_WIDTH_ADJUST 8 // cycles
  131. # else
  132. // ============ Standard setups ============
  133. # ifndef SELECT_SOFT_SERIAL_SPEED
  134. # define SELECT_SOFT_SERIAL_SPEED 1
  135. // 0: about 189kbps (Experimental only)
  136. // 1: about 137kbps (default)
  137. // 2: about 75kbps
  138. // 3: about 39kbps
  139. // 4: about 26kbps
  140. // 5: about 20kbps
  141. # endif
  142. # if __GNUC__ < 6
  143. # define TID_SEND_ADJUST 14
  144. # else
  145. # define TID_SEND_ADJUST 2
  146. # endif
  147. # if SELECT_SOFT_SERIAL_SPEED == 0
  148. // Very High speed
  149. # define SERIAL_DELAY 4 // micro sec
  150. # if __GNUC__ < 6
  151. # define READ_WRITE_START_ADJUST 33 // cycles
  152. # define READ_WRITE_WIDTH_ADJUST 3 // cycles
  153. # else
  154. # define READ_WRITE_START_ADJUST 34 // cycles
  155. # define READ_WRITE_WIDTH_ADJUST 7 // cycles
  156. # endif
  157. # elif SELECT_SOFT_SERIAL_SPEED == 1
  158. // High speed
  159. # define SERIAL_DELAY 6 // micro sec
  160. # if __GNUC__ < 6
  161. # define READ_WRITE_START_ADJUST 30 // cycles
  162. # define READ_WRITE_WIDTH_ADJUST 3 // cycles
  163. # else
  164. # define READ_WRITE_START_ADJUST 33 // cycles
  165. # define READ_WRITE_WIDTH_ADJUST 7 // cycles
  166. # endif
  167. # elif SELECT_SOFT_SERIAL_SPEED == 2
  168. // Middle speed
  169. # define SERIAL_DELAY 12 // micro sec
  170. # define READ_WRITE_START_ADJUST 30 // cycles
  171. # if __GNUC__ < 6
  172. # define READ_WRITE_WIDTH_ADJUST 3 // cycles
  173. # else
  174. # define READ_WRITE_WIDTH_ADJUST 7 // cycles
  175. # endif
  176. # elif SELECT_SOFT_SERIAL_SPEED == 3
  177. // Low speed
  178. # define SERIAL_DELAY 24 // micro sec
  179. # define READ_WRITE_START_ADJUST 30 // cycles
  180. # if __GNUC__ < 6
  181. # define READ_WRITE_WIDTH_ADJUST 3 // cycles
  182. # else
  183. # define READ_WRITE_WIDTH_ADJUST 7 // cycles
  184. # endif
  185. # elif SELECT_SOFT_SERIAL_SPEED == 4
  186. // Very Low speed
  187. # define SERIAL_DELAY 36 // micro sec
  188. # define READ_WRITE_START_ADJUST 30 // cycles
  189. # if __GNUC__ < 6
  190. # define READ_WRITE_WIDTH_ADJUST 3 // cycles
  191. # else
  192. # define READ_WRITE_WIDTH_ADJUST 7 // cycles
  193. # endif
  194. # elif SELECT_SOFT_SERIAL_SPEED == 5
  195. // Ultra Low speed
  196. # define SERIAL_DELAY 48 // micro sec
  197. # define READ_WRITE_START_ADJUST 30 // cycles
  198. # if __GNUC__ < 6
  199. # define READ_WRITE_WIDTH_ADJUST 3 // cycles
  200. # else
  201. # define READ_WRITE_WIDTH_ADJUST 7 // cycles
  202. # endif
  203. # else
  204. # error invalid SELECT_SOFT_SERIAL_SPEED value
  205. # endif /* SELECT_SOFT_SERIAL_SPEED */
  206. # endif /* SERIAL_DELAY */
  207. # define SERIAL_DELAY_HALF1 (SERIAL_DELAY / 2)
  208. # define SERIAL_DELAY_HALF2 (SERIAL_DELAY - SERIAL_DELAY / 2)
  209. # define SLAVE_INT_WIDTH_US 1
  210. # define SLAVE_INT_ACK_WIDTH_UNIT 2
  211. # define SLAVE_INT_ACK_WIDTH 4
  212. inline static void serial_delay(void) ALWAYS_INLINE;
  213. inline static void serial_delay(void) { _delay_us(SERIAL_DELAY); }
  214. inline static void serial_delay_half1(void) ALWAYS_INLINE;
  215. inline static void serial_delay_half1(void) { _delay_us(SERIAL_DELAY_HALF1); }
  216. inline static void serial_delay_half2(void) ALWAYS_INLINE;
  217. inline static void serial_delay_half2(void) { _delay_us(SERIAL_DELAY_HALF2); }
  218. inline static void serial_output(void) ALWAYS_INLINE;
  219. inline static void serial_output(void) { setPinOutput(SOFT_SERIAL_PIN); }
  220. // make the serial pin an input with pull-up resistor
  221. inline static void serial_input_with_pullup(void) ALWAYS_INLINE;
  222. inline static void serial_input_with_pullup(void) { setPinInputHigh(SOFT_SERIAL_PIN); }
  223. inline static uint8_t serial_read_pin(void) ALWAYS_INLINE;
  224. inline static uint8_t serial_read_pin(void) { return !!readPin(SOFT_SERIAL_PIN); }
  225. inline static void serial_low(void) ALWAYS_INLINE;
  226. inline static void serial_low(void) { writePinLow(SOFT_SERIAL_PIN); }
  227. inline static void serial_high(void) ALWAYS_INLINE;
  228. inline static void serial_high(void) { writePinHigh(SOFT_SERIAL_PIN); }
  229. void soft_serial_initiator_init(void) {
  230. serial_output();
  231. serial_high();
  232. }
  233. void soft_serial_target_init(void) {
  234. serial_input_with_pullup();
  235. // Enable INT0-INT7
  236. EIMSK |= EIMSK_BIT;
  237. EICRx &= EICRx_BIT;
  238. }
  239. // Used by the sender to synchronize timing with the reciver.
  240. static void sync_recv(void) NO_INLINE;
  241. static void sync_recv(void) {
  242. for (uint8_t i = 0; i < SERIAL_DELAY * 5 && serial_read_pin(); i++) {
  243. }
  244. // This shouldn't hang if the target disconnects because the
  245. // serial line will float to high if the target does disconnect.
  246. while (!serial_read_pin())
  247. ;
  248. }
  249. // Used by the reciver to send a synchronization signal to the sender.
  250. static void sync_send(void) NO_INLINE;
  251. static void sync_send(void) {
  252. serial_low();
  253. serial_delay();
  254. serial_high();
  255. }
  256. // Reads a byte from the serial line
  257. static uint8_t serial_read_chunk(uint8_t *pterrcount, uint8_t bit) NO_INLINE;
  258. static uint8_t serial_read_chunk(uint8_t *pterrcount, uint8_t bit) {
  259. uint8_t byte, i, p, pb;
  260. _delay_sub_us(READ_WRITE_START_ADJUST);
  261. for (i = 0, byte = 0, p = PARITY; i < bit; i++) {
  262. serial_delay_half1(); // read the middle of pulses
  263. if (serial_read_pin()) {
  264. byte = (byte << 1) | 1;
  265. p ^= 1;
  266. } else {
  267. byte = (byte << 1) | 0;
  268. p ^= 0;
  269. }
  270. _delay_sub_us(READ_WRITE_WIDTH_ADJUST);
  271. serial_delay_half2();
  272. }
  273. /* recive parity bit */
  274. serial_delay_half1(); // read the middle of pulses
  275. pb = serial_read_pin();
  276. _delay_sub_us(READ_WRITE_WIDTH_ADJUST);
  277. serial_delay_half2();
  278. *pterrcount += (p != pb) ? 1 : 0;
  279. return byte;
  280. }
  281. // Sends a byte with MSB ordering
  282. void serial_write_chunk(uint8_t data, uint8_t bit) NO_INLINE;
  283. void serial_write_chunk(uint8_t data, uint8_t bit) {
  284. uint8_t b, p;
  285. for (p = PARITY, b = 1 << (bit - 1); b; b >>= 1) {
  286. if (data & b) {
  287. serial_high();
  288. p ^= 1;
  289. } else {
  290. serial_low();
  291. p ^= 0;
  292. }
  293. serial_delay();
  294. }
  295. /* send parity bit */
  296. if (p & 1) {
  297. serial_high();
  298. } else {
  299. serial_low();
  300. }
  301. serial_delay();
  302. serial_low(); // sync_send() / senc_recv() need raise edge
  303. }
  304. static void serial_send_packet(uint8_t *buffer, uint8_t size) NO_INLINE;
  305. static void serial_send_packet(uint8_t *buffer, uint8_t size) {
  306. for (uint8_t i = 0; i < size; ++i) {
  307. uint8_t data;
  308. data = buffer[i];
  309. sync_send();
  310. serial_write_chunk(data, 8);
  311. }
  312. }
  313. static uint8_t serial_recive_packet(uint8_t *buffer, uint8_t size) NO_INLINE;
  314. static uint8_t serial_recive_packet(uint8_t *buffer, uint8_t size) {
  315. uint8_t pecount = 0;
  316. for (uint8_t i = 0; i < size; ++i) {
  317. uint8_t data;
  318. sync_recv();
  319. data = serial_read_chunk(&pecount, 8);
  320. buffer[i] = data;
  321. }
  322. return pecount == 0;
  323. }
  324. inline static void change_sender2reciver(void) {
  325. sync_send(); // 0
  326. serial_delay_half1(); // 1
  327. serial_low(); // 2
  328. serial_input_with_pullup(); // 2
  329. serial_delay_half1(); // 3
  330. }
  331. inline static void change_reciver2sender(void) {
  332. sync_recv(); // 0
  333. serial_delay(); // 1
  334. serial_low(); // 3
  335. serial_output(); // 3
  336. serial_delay_half1(); // 4
  337. }
  338. static inline uint8_t nibble_bits_count(uint8_t bits) {
  339. bits = (bits & 0x5) + (bits >> 1 & 0x5);
  340. bits = (bits & 0x3) + (bits >> 2 & 0x3);
  341. return bits;
  342. }
  343. // interrupt handle to be used by the target device
  344. ISR(SERIAL_PIN_INTERRUPT) {
  345. // recive transaction table index
  346. uint8_t tid, bits;
  347. uint8_t pecount = 0;
  348. sync_recv();
  349. bits = serial_read_chunk(&pecount, 8);
  350. tid = bits >> 3;
  351. bits = (bits & 7) != (nibble_bits_count(tid) & 7);
  352. if (bits || pecount > 0 || tid > NUM_TOTAL_TRANSACTIONS) {
  353. return;
  354. }
  355. serial_delay_half1();
  356. serial_high(); // response step1 low->high
  357. serial_output();
  358. _delay_sub_us(SLAVE_INT_ACK_WIDTH_UNIT * SLAVE_INT_ACK_WIDTH);
  359. split_transaction_desc_t *trans = &split_transaction_table[tid];
  360. serial_low(); // response step2 ack high->low
  361. // If the transaction has a callback, we can execute it now
  362. if (trans->slave_callback) {
  363. trans->slave_callback(trans->initiator2target_buffer_size, split_trans_initiator2target_buffer(trans), trans->target2initiator_buffer_size, split_trans_target2initiator_buffer(trans));
  364. }
  365. // target send phase
  366. if (trans->target2initiator_buffer_size > 0) serial_send_packet((uint8_t *)split_trans_target2initiator_buffer(trans), trans->target2initiator_buffer_size);
  367. // target switch to input
  368. change_sender2reciver();
  369. // target recive phase
  370. if (trans->initiator2target_buffer_size > 0) {
  371. if (serial_recive_packet((uint8_t *)split_trans_initiator2target_buffer(trans), trans->initiator2target_buffer_size)) {
  372. *trans->status = TRANSACTION_ACCEPTED;
  373. } else {
  374. *trans->status = TRANSACTION_DATA_ERROR;
  375. }
  376. } else {
  377. *trans->status = TRANSACTION_ACCEPTED;
  378. }
  379. sync_recv(); // weit initiator output to high
  380. }
  381. /////////
  382. // start transaction by initiator
  383. //
  384. // int soft_serial_transaction(int sstd_index)
  385. //
  386. // Returns:
  387. // TRANSACTION_END
  388. // TRANSACTION_NO_RESPONSE
  389. // TRANSACTION_DATA_ERROR
  390. // this code is very time dependent, so we need to disable interrupts
  391. int soft_serial_transaction(int sstd_index) {
  392. if (sstd_index > NUM_TOTAL_TRANSACTIONS) return TRANSACTION_TYPE_ERROR;
  393. split_transaction_desc_t *trans = &split_transaction_table[sstd_index];
  394. if (!trans->status) return TRANSACTION_TYPE_ERROR; // not registered
  395. cli();
  396. // signal to the target that we want to start a transaction
  397. serial_output();
  398. serial_low();
  399. _delay_us(SLAVE_INT_WIDTH_US);
  400. // send transaction table index
  401. int tid = (sstd_index << 3) | (7 & nibble_bits_count(sstd_index));
  402. sync_send();
  403. _delay_sub_us(TID_SEND_ADJUST);
  404. serial_write_chunk(tid, 8);
  405. serial_delay_half1();
  406. // wait for the target response (step1 low->high)
  407. serial_input_with_pullup();
  408. while (!serial_read_pin()) {
  409. _delay_sub_us(2);
  410. }
  411. // check if the target is present (step2 high->low)
  412. for (int i = 0; serial_read_pin(); i++) {
  413. if (i > SLAVE_INT_ACK_WIDTH + 1) {
  414. // slave failed to pull the line low, assume not present
  415. serial_output();
  416. serial_high();
  417. *trans->status = TRANSACTION_NO_RESPONSE;
  418. sei();
  419. return TRANSACTION_NO_RESPONSE;
  420. }
  421. _delay_sub_us(SLAVE_INT_ACK_WIDTH_UNIT);
  422. }
  423. // initiator recive phase
  424. // if the target is present syncronize with it
  425. if (trans->target2initiator_buffer_size > 0) {
  426. if (!serial_recive_packet((uint8_t *)split_trans_target2initiator_buffer(trans), trans->target2initiator_buffer_size)) {
  427. serial_output();
  428. serial_high();
  429. *trans->status = TRANSACTION_DATA_ERROR;
  430. sei();
  431. return TRANSACTION_DATA_ERROR;
  432. }
  433. }
  434. // initiator switch to output
  435. change_reciver2sender();
  436. // initiator send phase
  437. if (trans->initiator2target_buffer_size > 0) {
  438. serial_send_packet((uint8_t *)split_trans_initiator2target_buffer(trans), trans->initiator2target_buffer_size);
  439. }
  440. // always, release the line when not in use
  441. sync_send();
  442. *trans->status = TRANSACTION_END;
  443. sei();
  444. return TRANSACTION_END;
  445. }
  446. int soft_serial_get_and_clean_status(int sstd_index) {
  447. split_transaction_desc_t *trans = &split_transaction_table[sstd_index];
  448. cli();
  449. int retval = *trans->status;
  450. *trans->status = 0;
  451. ;
  452. sei();
  453. return retval;
  454. }
  455. #endif
  456. // Helix serial.c history
  457. // 2018-1-29 fork from let's split and add PD2, modify sync_recv() (#2308, bceffdefc)
  458. // 2018-6-28 bug fix master to slave comm and speed up (#3255, 1038bbef4)
  459. // (adjusted with avr-gcc 4.9.2)
  460. // 2018-7-13 remove USE_SERIAL_PD2 macro (#3374, f30d6dd78)
  461. // (adjusted with avr-gcc 4.9.2)
  462. // 2018-8-11 add support multi-type transaction (#3608, feb5e4aae)
  463. // (adjusted with avr-gcc 4.9.2)
  464. // 2018-10-21 fix serial and RGB animation conflict (#4191, 4665e4fff)
  465. // (adjusted with avr-gcc 7.3.0)
  466. // 2018-10-28 re-adjust compiler depend value of delay (#4269, 8517f8a66)
  467. // (adjusted with avr-gcc 5.4.0, 7.3.0)
  468. // 2018-12-17 copy to TOP/quantum/split_common/ and remove backward compatibility code (#4669)