serial.c 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541
  1. /*
  2. * WARNING: be careful changing this code, it is very timing dependent
  3. *
  4. * 2018-10-28 checked
  5. * avr-gcc 4.9.2
  6. * avr-gcc 5.4.0
  7. * avr-gcc 7.3.0
  8. */
  9. #ifndef F_CPU
  10. #define F_CPU 16000000
  11. #endif
  12. #include <avr/io.h>
  13. #include <avr/interrupt.h>
  14. #include <util/delay.h>
  15. #include <stddef.h>
  16. #include <stdbool.h>
  17. #include "serial.h"
  18. //#include <pro_micro.h>
  19. #ifdef SOFT_SERIAL_PIN
  20. #ifdef __AVR_ATmega32U4__
  21. // if using ATmega32U4 I2C, can not use PD0 and PD1 in soft serial.
  22. #ifdef USE_AVR_I2C
  23. #if SOFT_SERIAL_PIN == D0 || SOFT_SERIAL_PIN == D1
  24. #error Using ATmega32U4 I2C, so can not use PD0, PD1
  25. #endif
  26. #endif
  27. #define setPinInputHigh(pin) (DDRx_ADDRESS(pin) &= ~_BV((pin) & 0xF), \
  28. PORTx_ADDRESS(pin) |= _BV((pin) & 0xF))
  29. #define setPinOutput(pin) (DDRx_ADDRESS(pin) |= _BV((pin) & 0xF))
  30. #define writePinHigh(pin) (PORTx_ADDRESS(pin) |= _BV((pin) & 0xF))
  31. #define writePinLow(pin) (PORTx_ADDRESS(pin) &= ~_BV((pin) & 0xF))
  32. #define readPin(pin) ((bool)(PINx_ADDRESS(pin) & _BV((pin) & 0xF)))
  33. #if SOFT_SERIAL_PIN >= D0 && SOFT_SERIAL_PIN <= D3
  34. #if SOFT_SERIAL_PIN == D0
  35. #define EIMSK_BIT _BV(INT0)
  36. #define EICRx_BIT (~(_BV(ISC00) | _BV(ISC01)))
  37. #define SERIAL_PIN_INTERRUPT INT0_vect
  38. #elif SOFT_SERIAL_PIN == D1
  39. #define EIMSK_BIT _BV(INT1)
  40. #define EICRx_BIT (~(_BV(ISC10) | _BV(ISC11)))
  41. #define SERIAL_PIN_INTERRUPT INT1_vect
  42. #elif SOFT_SERIAL_PIN == D2
  43. #define EIMSK_BIT _BV(INT2)
  44. #define EICRx_BIT (~(_BV(ISC20) | _BV(ISC21)))
  45. #define SERIAL_PIN_INTERRUPT INT2_vect
  46. #elif SOFT_SERIAL_PIN == D3
  47. #define EIMSK_BIT _BV(INT3)
  48. #define EICRx_BIT (~(_BV(ISC30) | _BV(ISC31)))
  49. #define SERIAL_PIN_INTERRUPT INT3_vect
  50. #endif
  51. #elif SOFT_SERIAL_PIN == E6
  52. #define EIMSK_BIT _BV(INT6)
  53. #define EICRx_BIT (~(_BV(ISC60) | _BV(ISC61)))
  54. #define SERIAL_PIN_INTERRUPT INT6_vect
  55. #else
  56. #error invalid SOFT_SERIAL_PIN value
  57. #endif
  58. #else
  59. #error serial.c now support ATmega32U4 only
  60. #endif
  61. #define ALWAYS_INLINE __attribute__((always_inline))
  62. #define NO_INLINE __attribute__((noinline))
  63. #define _delay_sub_us(x) __builtin_avr_delay_cycles(x)
  64. // parity check
  65. #define ODD_PARITY 1
  66. #define EVEN_PARITY 0
  67. #define PARITY EVEN_PARITY
  68. #ifdef SERIAL_DELAY
  69. // custom setup in config.h
  70. // #define TID_SEND_ADJUST 2
  71. // #define SERIAL_DELAY 6 // micro sec
  72. // #define READ_WRITE_START_ADJUST 30 // cycles
  73. // #define READ_WRITE_WIDTH_ADJUST 8 // cycles
  74. #else
  75. // ============ Standard setups ============
  76. #ifndef SELECT_SOFT_SERIAL_SPEED
  77. #define SELECT_SOFT_SERIAL_SPEED 1
  78. // 0: about 189kbps (Experimental only)
  79. // 1: about 137kbps (default)
  80. // 2: about 75kbps
  81. // 3: about 39kbps
  82. // 4: about 26kbps
  83. // 5: about 20kbps
  84. #endif
  85. #if __GNUC__ < 6
  86. #define TID_SEND_ADJUST 14
  87. #else
  88. #define TID_SEND_ADJUST 2
  89. #endif
  90. #if SELECT_SOFT_SERIAL_SPEED == 0
  91. // Very High speed
  92. #define SERIAL_DELAY 4 // micro sec
  93. #if __GNUC__ < 6
  94. #define READ_WRITE_START_ADJUST 33 // cycles
  95. #define READ_WRITE_WIDTH_ADJUST 3 // cycles
  96. #else
  97. #define READ_WRITE_START_ADJUST 34 // cycles
  98. #define READ_WRITE_WIDTH_ADJUST 7 // cycles
  99. #endif
  100. #elif SELECT_SOFT_SERIAL_SPEED == 1
  101. // High speed
  102. #define SERIAL_DELAY 6 // micro sec
  103. #if __GNUC__ < 6
  104. #define READ_WRITE_START_ADJUST 30 // cycles
  105. #define READ_WRITE_WIDTH_ADJUST 3 // cycles
  106. #else
  107. #define READ_WRITE_START_ADJUST 33 // cycles
  108. #define READ_WRITE_WIDTH_ADJUST 7 // cycles
  109. #endif
  110. #elif SELECT_SOFT_SERIAL_SPEED == 2
  111. // Middle speed
  112. #define SERIAL_DELAY 12 // micro sec
  113. #define READ_WRITE_START_ADJUST 30 // cycles
  114. #if __GNUC__ < 6
  115. #define READ_WRITE_WIDTH_ADJUST 3 // cycles
  116. #else
  117. #define READ_WRITE_WIDTH_ADJUST 7 // cycles
  118. #endif
  119. #elif SELECT_SOFT_SERIAL_SPEED == 3
  120. // Low speed
  121. #define SERIAL_DELAY 24 // micro sec
  122. #define READ_WRITE_START_ADJUST 30 // cycles
  123. #if __GNUC__ < 6
  124. #define READ_WRITE_WIDTH_ADJUST 3 // cycles
  125. #else
  126. #define READ_WRITE_WIDTH_ADJUST 7 // cycles
  127. #endif
  128. #elif SELECT_SOFT_SERIAL_SPEED == 4
  129. // Very Low speed
  130. #define SERIAL_DELAY 36 // micro sec
  131. #define READ_WRITE_START_ADJUST 30 // cycles
  132. #if __GNUC__ < 6
  133. #define READ_WRITE_WIDTH_ADJUST 3 // cycles
  134. #else
  135. #define READ_WRITE_WIDTH_ADJUST 7 // cycles
  136. #endif
  137. #elif SELECT_SOFT_SERIAL_SPEED == 5
  138. // Ultra Low speed
  139. #define SERIAL_DELAY 48 // micro sec
  140. #define READ_WRITE_START_ADJUST 30 // cycles
  141. #if __GNUC__ < 6
  142. #define READ_WRITE_WIDTH_ADJUST 3 // cycles
  143. #else
  144. #define READ_WRITE_WIDTH_ADJUST 7 // cycles
  145. #endif
  146. #else
  147. #error invalid SELECT_SOFT_SERIAL_SPEED value
  148. #endif /* SELECT_SOFT_SERIAL_SPEED */
  149. #endif /* SERIAL_DELAY */
  150. #define SERIAL_DELAY_HALF1 (SERIAL_DELAY/2)
  151. #define SERIAL_DELAY_HALF2 (SERIAL_DELAY - SERIAL_DELAY/2)
  152. #define SLAVE_INT_WIDTH_US 1
  153. #ifndef SERIAL_USE_MULTI_TRANSACTION
  154. #define SLAVE_INT_RESPONSE_TIME SERIAL_DELAY
  155. #else
  156. #define SLAVE_INT_ACK_WIDTH_UNIT 2
  157. #define SLAVE_INT_ACK_WIDTH 4
  158. #endif
  159. static SSTD_t *Transaction_table = NULL;
  160. static uint8_t Transaction_table_size = 0;
  161. inline static void serial_delay(void) ALWAYS_INLINE;
  162. inline static
  163. void serial_delay(void) {
  164. _delay_us(SERIAL_DELAY);
  165. }
  166. inline static void serial_delay_half1(void) ALWAYS_INLINE;
  167. inline static
  168. void serial_delay_half1(void) {
  169. _delay_us(SERIAL_DELAY_HALF1);
  170. }
  171. inline static void serial_delay_half2(void) ALWAYS_INLINE;
  172. inline static
  173. void serial_delay_half2(void) {
  174. _delay_us(SERIAL_DELAY_HALF2);
  175. }
  176. inline static void serial_output(void) ALWAYS_INLINE;
  177. inline static
  178. void serial_output(void) {
  179. setPinOutput(SOFT_SERIAL_PIN);
  180. }
  181. // make the serial pin an input with pull-up resistor
  182. inline static void serial_input_with_pullup(void) ALWAYS_INLINE;
  183. inline static
  184. void serial_input_with_pullup(void) {
  185. setPinInputHigh(SOFT_SERIAL_PIN);
  186. }
  187. inline static uint8_t serial_read_pin(void) ALWAYS_INLINE;
  188. inline static
  189. uint8_t serial_read_pin(void) {
  190. return !! readPin(SOFT_SERIAL_PIN);
  191. }
  192. inline static void serial_low(void) ALWAYS_INLINE;
  193. inline static
  194. void serial_low(void) {
  195. writePinLow(SOFT_SERIAL_PIN);
  196. }
  197. inline static void serial_high(void) ALWAYS_INLINE;
  198. inline static
  199. void serial_high(void) {
  200. writePinHigh(SOFT_SERIAL_PIN);
  201. }
  202. void soft_serial_initiator_init(SSTD_t *sstd_table, int sstd_table_size)
  203. {
  204. Transaction_table = sstd_table;
  205. Transaction_table_size = (uint8_t)sstd_table_size;
  206. serial_output();
  207. serial_high();
  208. }
  209. void soft_serial_target_init(SSTD_t *sstd_table, int sstd_table_size)
  210. {
  211. Transaction_table = sstd_table;
  212. Transaction_table_size = (uint8_t)sstd_table_size;
  213. serial_input_with_pullup();
  214. // Enable INT0-INT3,INT6
  215. EIMSK |= EIMSK_BIT;
  216. #if SOFT_SERIAL_PIN == E6
  217. // Trigger on falling edge of INT6
  218. EICRB &= EICRx_BIT;
  219. #else
  220. // Trigger on falling edge of INT0-INT3
  221. EICRA &= EICRx_BIT;
  222. #endif
  223. }
  224. // Used by the sender to synchronize timing with the reciver.
  225. static void sync_recv(void) NO_INLINE;
  226. static
  227. void sync_recv(void) {
  228. for (uint8_t i = 0; i < SERIAL_DELAY*5 && serial_read_pin(); i++ ) {
  229. }
  230. // This shouldn't hang if the target disconnects because the
  231. // serial line will float to high if the target does disconnect.
  232. while (!serial_read_pin());
  233. }
  234. // Used by the reciver to send a synchronization signal to the sender.
  235. static void sync_send(void) NO_INLINE;
  236. static
  237. void sync_send(void) {
  238. serial_low();
  239. serial_delay();
  240. serial_high();
  241. }
  242. // Reads a byte from the serial line
  243. static uint8_t serial_read_chunk(uint8_t *pterrcount, uint8_t bit) NO_INLINE;
  244. static uint8_t serial_read_chunk(uint8_t *pterrcount, uint8_t bit) {
  245. uint8_t byte, i, p, pb;
  246. _delay_sub_us(READ_WRITE_START_ADJUST);
  247. for( i = 0, byte = 0, p = PARITY; i < bit; i++ ) {
  248. serial_delay_half1(); // read the middle of pulses
  249. if( serial_read_pin() ) {
  250. byte = (byte << 1) | 1; p ^= 1;
  251. } else {
  252. byte = (byte << 1) | 0; p ^= 0;
  253. }
  254. _delay_sub_us(READ_WRITE_WIDTH_ADJUST);
  255. serial_delay_half2();
  256. }
  257. /* recive parity bit */
  258. serial_delay_half1(); // read the middle of pulses
  259. pb = serial_read_pin();
  260. _delay_sub_us(READ_WRITE_WIDTH_ADJUST);
  261. serial_delay_half2();
  262. *pterrcount += (p != pb)? 1 : 0;
  263. return byte;
  264. }
  265. // Sends a byte with MSB ordering
  266. void serial_write_chunk(uint8_t data, uint8_t bit) NO_INLINE;
  267. void serial_write_chunk(uint8_t data, uint8_t bit) {
  268. uint8_t b, p;
  269. for( p = PARITY, b = 1<<(bit-1); b ; b >>= 1) {
  270. if(data & b) {
  271. serial_high(); p ^= 1;
  272. } else {
  273. serial_low(); p ^= 0;
  274. }
  275. serial_delay();
  276. }
  277. /* send parity bit */
  278. if(p & 1) { serial_high(); }
  279. else { serial_low(); }
  280. serial_delay();
  281. serial_low(); // sync_send() / senc_recv() need raise edge
  282. }
  283. static void serial_send_packet(uint8_t *buffer, uint8_t size) NO_INLINE;
  284. static
  285. void serial_send_packet(uint8_t *buffer, uint8_t size) {
  286. for (uint8_t i = 0; i < size; ++i) {
  287. uint8_t data;
  288. data = buffer[i];
  289. sync_send();
  290. serial_write_chunk(data,8);
  291. }
  292. }
  293. static uint8_t serial_recive_packet(uint8_t *buffer, uint8_t size) NO_INLINE;
  294. static
  295. uint8_t serial_recive_packet(uint8_t *buffer, uint8_t size) {
  296. uint8_t pecount = 0;
  297. for (uint8_t i = 0; i < size; ++i) {
  298. uint8_t data;
  299. sync_recv();
  300. data = serial_read_chunk(&pecount, 8);
  301. buffer[i] = data;
  302. }
  303. return pecount == 0;
  304. }
  305. inline static
  306. void change_sender2reciver(void) {
  307. sync_send(); //0
  308. serial_delay_half1(); //1
  309. serial_low(); //2
  310. serial_input_with_pullup(); //2
  311. serial_delay_half1(); //3
  312. }
  313. inline static
  314. void change_reciver2sender(void) {
  315. sync_recv(); //0
  316. serial_delay(); //1
  317. serial_low(); //3
  318. serial_output(); //3
  319. serial_delay_half1(); //4
  320. }
  321. static inline uint8_t nibble_bits_count(uint8_t bits)
  322. {
  323. bits = (bits & 0x5) + (bits >> 1 & 0x5);
  324. bits = (bits & 0x3) + (bits >> 2 & 0x3);
  325. return bits;
  326. }
  327. // interrupt handle to be used by the target device
  328. ISR(SERIAL_PIN_INTERRUPT) {
  329. #ifndef SERIAL_USE_MULTI_TRANSACTION
  330. serial_low();
  331. serial_output();
  332. SSTD_t *trans = Transaction_table;
  333. #else
  334. // recive transaction table index
  335. uint8_t tid, bits;
  336. uint8_t pecount = 0;
  337. sync_recv();
  338. bits = serial_read_chunk(&pecount,7);
  339. tid = bits>>3;
  340. bits = (bits&7) != nibble_bits_count(tid);
  341. if( bits || pecount> 0 || tid > Transaction_table_size ) {
  342. return;
  343. }
  344. serial_delay_half1();
  345. serial_high(); // response step1 low->high
  346. serial_output();
  347. _delay_sub_us(SLAVE_INT_ACK_WIDTH_UNIT*SLAVE_INT_ACK_WIDTH);
  348. SSTD_t *trans = &Transaction_table[tid];
  349. serial_low(); // response step2 ack high->low
  350. #endif
  351. // target send phase
  352. if( trans->target2initiator_buffer_size > 0 )
  353. serial_send_packet((uint8_t *)trans->target2initiator_buffer,
  354. trans->target2initiator_buffer_size);
  355. // target switch to input
  356. change_sender2reciver();
  357. // target recive phase
  358. if( trans->initiator2target_buffer_size > 0 ) {
  359. if (serial_recive_packet((uint8_t *)trans->initiator2target_buffer,
  360. trans->initiator2target_buffer_size) ) {
  361. *trans->status = TRANSACTION_ACCEPTED;
  362. } else {
  363. *trans->status = TRANSACTION_DATA_ERROR;
  364. }
  365. } else {
  366. *trans->status = TRANSACTION_ACCEPTED;
  367. }
  368. sync_recv(); //weit initiator output to high
  369. }
  370. /////////
  371. // start transaction by initiator
  372. //
  373. // int soft_serial_transaction(int sstd_index)
  374. //
  375. // Returns:
  376. // TRANSACTION_END
  377. // TRANSACTION_NO_RESPONSE
  378. // TRANSACTION_DATA_ERROR
  379. // this code is very time dependent, so we need to disable interrupts
  380. #ifndef SERIAL_USE_MULTI_TRANSACTION
  381. int soft_serial_transaction(void) {
  382. SSTD_t *trans = Transaction_table;
  383. #else
  384. int soft_serial_transaction(int sstd_index) {
  385. if( sstd_index > Transaction_table_size )
  386. return TRANSACTION_TYPE_ERROR;
  387. SSTD_t *trans = &Transaction_table[sstd_index];
  388. #endif
  389. cli();
  390. // signal to the target that we want to start a transaction
  391. serial_output();
  392. serial_low();
  393. _delay_us(SLAVE_INT_WIDTH_US);
  394. #ifndef SERIAL_USE_MULTI_TRANSACTION
  395. // wait for the target response
  396. serial_input_with_pullup();
  397. _delay_us(SLAVE_INT_RESPONSE_TIME);
  398. // check if the target is present
  399. if (serial_read_pin()) {
  400. // target failed to pull the line low, assume not present
  401. serial_output();
  402. serial_high();
  403. *trans->status = TRANSACTION_NO_RESPONSE;
  404. sei();
  405. return TRANSACTION_NO_RESPONSE;
  406. }
  407. #else
  408. // send transaction table index
  409. int tid = (sstd_index<<3) | (7 & nibble_bits_count(sstd_index));
  410. sync_send();
  411. _delay_sub_us(TID_SEND_ADJUST);
  412. serial_write_chunk(tid, 7);
  413. serial_delay_half1();
  414. // wait for the target response (step1 low->high)
  415. serial_input_with_pullup();
  416. while( !serial_read_pin() ) {
  417. _delay_sub_us(2);
  418. }
  419. // check if the target is present (step2 high->low)
  420. for( int i = 0; serial_read_pin(); i++ ) {
  421. if (i > SLAVE_INT_ACK_WIDTH + 1) {
  422. // slave failed to pull the line low, assume not present
  423. serial_output();
  424. serial_high();
  425. *trans->status = TRANSACTION_NO_RESPONSE;
  426. sei();
  427. return TRANSACTION_NO_RESPONSE;
  428. }
  429. _delay_sub_us(SLAVE_INT_ACK_WIDTH_UNIT);
  430. }
  431. #endif
  432. // initiator recive phase
  433. // if the target is present syncronize with it
  434. if( trans->target2initiator_buffer_size > 0 ) {
  435. if (!serial_recive_packet((uint8_t *)trans->target2initiator_buffer,
  436. trans->target2initiator_buffer_size) ) {
  437. serial_output();
  438. serial_high();
  439. *trans->status = TRANSACTION_DATA_ERROR;
  440. sei();
  441. return TRANSACTION_DATA_ERROR;
  442. }
  443. }
  444. // initiator switch to output
  445. change_reciver2sender();
  446. // initiator send phase
  447. if( trans->initiator2target_buffer_size > 0 ) {
  448. serial_send_packet((uint8_t *)trans->initiator2target_buffer,
  449. trans->initiator2target_buffer_size);
  450. }
  451. // always, release the line when not in use
  452. sync_send();
  453. *trans->status = TRANSACTION_END;
  454. sei();
  455. return TRANSACTION_END;
  456. }
  457. #ifdef SERIAL_USE_MULTI_TRANSACTION
  458. int soft_serial_get_and_clean_status(int sstd_index) {
  459. SSTD_t *trans = &Transaction_table[sstd_index];
  460. cli();
  461. int retval = *trans->status;
  462. *trans->status = 0;;
  463. sei();
  464. return retval;
  465. }
  466. #endif
  467. #endif
  468. // Helix serial.c history
  469. // 2018-1-29 fork from let's split and add PD2, modify sync_recv() (#2308, bceffdefc)
  470. // 2018-6-28 bug fix master to slave comm and speed up (#3255, 1038bbef4)
  471. // (adjusted with avr-gcc 4.9.2)
  472. // 2018-7-13 remove USE_SERIAL_PD2 macro (#3374, f30d6dd78)
  473. // (adjusted with avr-gcc 4.9.2)
  474. // 2018-8-11 add support multi-type transaction (#3608, feb5e4aae)
  475. // (adjusted with avr-gcc 4.9.2)
  476. // 2018-10-21 fix serial and RGB animation conflict (#4191, 4665e4fff)
  477. // (adjusted with avr-gcc 7.3.0)
  478. // 2018-10-28 re-adjust compiler depend value of delay (#4269, 8517f8a66)
  479. // (adjusted with avr-gcc 5.4.0, 7.3.0)
  480. // 2018-12-17 copy to TOP/quantum/split_common/ and remove backward compatibility code (#4669)